1. Field of the Invention
This technology relates to integrated circuit memory technologies, including technologies using phase change materials.
2. Description of Related Art
Many three dimensional (3D) memory concepts have been proposed in order to make high density memory. Li et al., “Evaluation of SiO2 Antifuse in a 3D-OTP Memory,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, SEPTEMBER 2004, describes a polysilicon diode and an anti-fuse arranged as a memory cell. Sasago et al., “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pages 24-25, describes a polysilicon diode and a phase change element arranged as a memory cell. Kau et al., “A stackable cross point phase change memory,” IEDM09-617, (2009) pages 27.1.1 to 27.1.4, describes a memory cell including an ovonic threshold switch OTS as an isolation device with a phase change element. These technologies rely on a combination of an isolation device and a memory element to construct the memory cell. The isolation device adds extra processes and thickness and/or area to the memory structure. Also, the isolation device/memory element approach is not suitable for many 3D memory structures, including so called Bit Cost Scalable BiCS structures and other 3D memory structures that include a large number of memory layers.
In Chen et al., “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device,” IEDM 03-905, (2003), pages 37.4.1 to 37.4.4, a so-called zero transistor/one resistor 0T/1R memory cell is described using a phase change element that does not include a separate isolation device. (See, also, U.S. Pat. No. 7,236,394). But 0T/1R memory cell described in Chen et al. can only be used in small arrays, because after completing the manufacture of the device, the phase change element is in the low resistance crystalline phase. This low resistance phase makes the first programming step for the array difficult, due to the inability to fully isolate unselected cells during the first programming cycle. Also, the 0T/1R cell technology described by Chen et al. includes a relatively large contact area between the electrodes and the phase change element, so that the reset current must be relatively high. Furthermore, because of large leakage current from unselected cells, the size of the array must be very limited in order to preserve the read margins. Thus, the Chen et al. 0T/1R cell has not been successfully deployed for high density memory.
Therefore, it is desirable to provide a memory technology that is suitable for high density structures, and is easily manufactured.